Embedded PC (EPC) board setup information

if (ralph | marshall)
goto setup;

Table of Contents

Existing I/O port addresses
Our I/O Port Addresses
Memory Layout for iRMXIII-based Image
BIOS & Ethernet Setup screens
PNET Modification Instructions
MBCD Modification Instructions

Revision History:
09-Jul-1997 Integrate Ethernet BIOS setup.
08-Jul-1997 Pnet Board Changes.
31-Jul-1997 Update interrupts; IRQ12 can't be used. Move on-board Kisnet to IRQ3.
11-Aug-1997 Change protected mode Multibus access to encompass both BIT3 memories & the Computrol.

Just some notes I left behind.
  1. p. 7-12 SBX I/O command recovery is programmable. Goes through ISA bus.
  2. p. 4-19, 7-12 Multibus I/O window info.
  3. p. 6-3 The SBX i.e. Kisnet goes through the ISA bus and thus can't

  4. access > 16 Mbytes. Ethernet also goes through the ISA bus
    so can't boot an image > 16 Mbytes. Probably OK.
  5. p. 6-5 Video DRAM. We can't make this dual-ported? Right! p. 8-1 says

  6. so!! Well, it implies you shouldn't but it would be allowed??
  7. Should we map dual-ported memory only to 640K i.e. to 9FFFF with video

  8. DRAM going from A0000 - C0000. Video BIOS (p. 6-2) goes from
    C0000 - C8000 Yes!!! We can afford to throw away the last 1/4 Mbyte of the 1st Mbyte
    Only map dual-ported Multibus to A000 as we do now.
  9. Chapter 5 PCI Device configuration. Shows how CDC, SIO etc. are mapped into

  10. the PCI device I/O space.


Unlike previous MBI boards, not all interrupts are configurable. Page 8-3 of the Preliminary User's Guide shows the situation. Specifically, there are no jumper options for the NMI. Additionally, IRQ 0 (timer), IRQ6 (floppy??), IRQ8 (real-time clock) and IRQ13 (floating point error) are not configurable. Oh yeah? 
Int    Description              Configuration               Jumpers
---    -----------              -------------               -------

IRQ0   iRMXII/iRMXIII 100Hz.    PIT Timer 1 counter 0        None (internal)

IRQ1   Keyboard/Erstwhile       MINT0-IRQ1                   E27-E50

IRQ3   Onboard Kisnet           SBXAIRQ0-IRQ3                E23-E26

IRQ4   Computrol.               MINT4-IRQ4                   E34-E35

IRQ5   Incoming 2nd PNET.       MINT3-IRQ5                   E36-E37

IRQ6   Floppy                   E72                          None
IRQ7   Triggerable by CPU       MINT7-E60                    E61-E60
                                MBINT7 thru port 75 Bit 0    E120-E119

IRQ8   Realtime Clock           None                         None

IRQ9   Ethernet                 E24                          None

IRQ10  Multibus error interrupt MB_ERRINT-IRQ10              E43-E42        E42-MINT5                    E42-E47

IRQ11  Camac lam via PNET       MINT1-IRQ11                  E59-E44

IRQ12  This interrupt can't be used without modifying the board. There 
       is a direct inverter coming out of the keyboard/mouse controller 
       for the mouse interrupt request. The documentation and jumpers are
       set so as to make one think it can be used but the BIOS menu does
       not show it as available.

       If we get desperate and need another interrupt, since we don't
       use the mouse we could clip pin 6 of U29 for the mouse interrupt
       request inverter in which case IRQ12 should be available.

IRQ13  Floating Point Error     None                         None

IRQ14  CD/Kisnet Board          MINT5-IRQ14                  E47-E48   

IRQ15  BCOM CD board            MINT6-IRQ14                  E45-E46

Existing I/O port addresses. 

  0000-000F        SIO - DMA controller 1
  0020-0021        SIO - Interrupt controller 1
  0022-0023        AIP - Configuration registers
  0040-0043        SIO - Timer

  0060  or               Keyboard data
  0060             SIO - Reset Ubus IRQ12 if enabled

  0061             SIO - NMI status & control
  0064                   Keyboard status & control

  0070 bit 7       SIO - NMI enable
  0070 bits 6:0          Realtime clock address
  0071                   Realtime clock data

  0073                   Standard PC configuration register
                         Bit 7 - RW Flash write enable.
                         Bit 6 - WO CPU detection bit 1.
                                 RO Pentium Overdrive installed.
                         Bit 5 - WO CPU detection bit 0.
                                 RO CPU with floating pt installed.
                         Bit 4 - RW IDE enabled. If not IRQ14 is available.
                         Bit 3 - RW Speaker enable.
                         Bit 2 - RW Software status. CDC turbo mode?
                         Bit 1 - RO Hardware status. Password enabled.
                         Bit 0 - RO Hardware status. Erase CMOS.

  0075                   Multibus configuration register.
                         Bit 7 - RO Software status. CPU type locked.
                         Bit 6 - RW User expansion BIOS enabled.
                         Bit 5 - RW Reserved.
                         Bit 4 - RO Software status. CPU cache type.
                         Bit 3 - RW Clear parity interrupt.
                         Bit 2 - RW Force parity error.
                         Bit 1 - RW Multibus interrupt 2 on high transition.
                         Bit 0 - RW Multibus interrupt 1 on high transition.

  0078-007B        SIO - BIOS timer
  0080-0090        SIO - DMA page registers
  0092             SIO - ALT_RQST# and ALT_A20 control ??
  0094-009F        SIO - DMA page registers
  00A0-00A1        SIO - Interrupt controller 2
  00C0-00DE        SIO - DMA controller 2
  00F0             SIO - Coprocessor error
  0170-0177              RZ1000 - IDE secondary

  0180-019E              SBX I/O A
                             0180 Onboard Kisnet data
                             0181 Onboard Kisnet command
  01A0-01BE              SBX I/O B

  01F0-01F7              RZ1000 - IDE primary

  0278-027F        AIP - Parallel port LPT3 (if configured)
  02F8-02FF        AIP - Serial port B: COM2
  0300-030F              82595TX Ethernet controller
  0378--37F        AIP - Parallel port LPT2 (if configured)
  03BC-03BF        AIP - Parallel port LPT1 (default)
  03C0-03DF              PCI VGA
  03F0-03F7        AIP - Floppy disk controller
  03F8-03FF        AIP - Serial port A COM1 (default)
  040A-043C        SIO - DMA Scatter/Gather
  040B             SIO - DMA extended mode 1
  0481-048B        SIO - DMA high page registers
  04D0-04D1        SIO - Interrupt 1 & 2 edge/level control
  04D6             SIO - DMA extended mode 2

  0678-067A        AIP - Parallel port LPT3 ECP mode
  0778-077A        AIP - Parallel port LPT2 ECP mode
  07BC-07BE        AIP - Parallel port LPT1 ECP mode

  0CF8-0CFA              CDC control registers

  0D00-FBFF              Multibus I/O window
  FC00-FFFF              Available for PCI devices:
                         - SCSI-2 requires 256 bytes starting at FC00
                           (if enabled)

Our I/O Port Addresses 

We map the Multibus I/O window 1000 + 18FF to I/O space 0 - 8FF so we don't have to change any of our interfaces. Instead, we add 1000H to all of our I/O addresses if we're running on the EPC board. e.g. the MBCD instead of being port 120 is now 1120.
  0120                   MBCD package pointer FIFO.
  0122                   MBCD TDV register.
  0180-019E              SBX I/O A
                             0180 Onboard Kisnet data
                             0181 Onboard Kisnet command
   ---                   Matrox display board (FB31 only).
  0400             PNET triggerable interrupt 0 (write=assert; read=deassert).
  0402             PNET triggerable interrupt 1 (write=assert; read=deassert).
  0404             PNET triggerable interrupt 2 (write=assert; read=deassert).
  0406             PNET triggerable interrupt 3 (write=assert; read=deassert).
  0408             PNET read/write buffer memory.
  040A             PNET reset buffer memory pointer (write).
  040C             PNET generate Multibus reset (write).
  040E             PNET read status (upper byte) and bytecount (lower byte).
  0410             PNET read/write SSA.
  0412             PNET stop modem (write).
  0414             PNET start modem (write).
  0416             PNET reset PNET module only.
  0418             PNET disable deadman reset (write).
  041A             PNET enable deadman reset (write).
  041C             PNET retrigger deadman (write).
  041C             PNET assert RTS (read).
  041E             PNET deassert RTS (read).

   ---             2nd PNET module (receiver or sender).

   ---             BIT3 shared memory board (MP00 & MP01 only) for MPS.

   ---             BIT3 shared memory board (MP00 & MP01 only) for PEPII.

  0480             FSK modem (companion to Computrol).

  0500-0502        CD/KISnet board, socket #1, data/command.
  0540-0542        CD/KISnet board, socket #3, data/command.
  0560-0562        CD/KISnet board, socket #4, data/command.
  0580-0582        CD/KISnet board, socket #5, data/command.
  05A0-05A2        CD/KISnet board, socket #6, data/command.

  0600-0604        CD/BCOM board, Master #1, data/command.
  06C0-06D2        CD/BCOM board, PIC addresses.

Memory Layout for iRMXIII-based Image 

      Dual-port ram (go past 640K)          0   09FFFF   .5 Mbytes
      Reserved for SDM                      0     0FFF
      PASSTHRU                           1000     10FF
      ComputrolRAMdump                   1100     11FF
      PROM386 ram area                   1200     5FFF
      SLCnet driver buffers              1400     9BFF
      NMI_global common                 0AE80    0B1FF
      MBCD memory pool                  0B200   09FFFF   0.61 Mbyte
      Everything else (*)              110000   2FFFFF   2.10 Mbyte
      iRMXIII memory pool              300000   7FFFFF   5.00 Mbytes
The BIT3 and Computrol RAM are configured as a Protected Mode Multibus window and are addressed above 64 Mbytes. Only the lower 20 bits go to the Multibus so they must be beyond what we map for the MBCD.
      BIT3 shared memory (MPS)         40C0000   FC0C7FFF
      Computrol ram                    40DF800   FC0DFFFF
      BIT3 shared memory (PEPII)       40E0000   FC0FFFFF

 (*) "Everything else" includes:  a. GDT, IDT, 1 LDT, and 2 TSS's.
                                  b. iRMXIII nucleus + SDM + SDB code & data.
                                  c. SLCnet Driver code.
                                  d. MD386 code & data.
                                  e. SLC AP ("subjobs", code & static data).
Note that the MBCD memory pool (which must be readable and writable both by the CPU and by the MBCD) must be within the dual-port ram, and the BIT3 shared memory and the Computrol ram must be outside the dual-port ram (the latter are addressed using addresses larger than the on-board ram, and our Multibus-I drops all but the low-order 20 address bits). Each of the MBCD memory pool, the BIT3 shared memory, and the Computrol ram must be withinthe "0th" Megabyte of Multibus-I memory space.

!!!!!!!!!!!!!!!!!!!!!!!Marshall & Ralph start here!!!!!!!!!!!!
BIOS & Ethernet Setup Screens 
In this section we configure the BIOS parameters and the Ethernet chip.
Before starting insure that:
  1. The wire wrap for the MI MINT0->IRQ1 pins E50-E27 is not installed. This interrupt is used by the keyboard so you can't enter setup with it in place.
  2. The User ROM Expansion BIOS flash is not installed. BIOS will check for its signature and transfer control to it if detected. Since our code never returns to BIOS, you'll be like Charley on the MTA.
  3. The video card is mounted on the EPC and the video, keyboard, ethernet and floppy cables are connected.

When the board is powered up and the startup screen appears, press F1 to enter setup. Update the current system date & time and disable all disks except for Floppy A which we'll need to run softset to set up the Etherexpress chip. For Floppy A: choose type 1.44 Mb 3 1/2 inch.


Here's where we get to the important stuff. The advanced screen itself just gives CPU type, speed and cache size.


Don't set passwords. We remove jumpers E73-E78 so its disabled.

Save changes and exit for the first time so we can configure the ethernet.


In order to configure the ethernet we need to first boot DOS and then run Softset2.


When the system comes up, press F1 to again enter BIOS setup.

This time disable Floppy A:

Disable the floppy interface since it's not needed for normal EPC running.


Save & exit BIOS for the last time.


  1. Insert the latest version of the boot flash in the User ROM Expansion BIOS

  2. socket. This is the second empty socket from the system BIOS.
  3.  As your last act, install the jumper from E50-E27 which is the NMI-as-MI and you're ready for prime time.


 E27 - E50:  MINT0     -> IRQ1      Former NMI; Former keyboard interrupt.
 E23 - E26:  SBXAIRQ0  -> IRQ3      Onboard KISnet
 E34 - E35:  MINT4     -> IRQ4      Computrol
 E36 - E37:  MINT3     -> IRQ5      Incoming 2nd PNET

 E61 - E60:  MINT7     -> IRQ7      Triggerable by CPU
 E43 - E42:  MB_ERRINT -> IRQ10     Multibus error interrupt
 E59 - E44:  MINT1     -> IRQ11     Camac lam via PNET
 E47 - E48:  MINT5     -> IRQ14     CD/KISnet board
 E45 - E46:  MINT6     -> IRQ15     BCOM board

 E55 - E70:  +12V      -> ENTPROG   +12V to Ethernet expansion flash
 E54 - E69:  +12V      -> ENLPROG   +12V to User enlarged BIOS flash
 E53 - E68:  +12V      -> BIOSPROG  +12V to BIOS flash
 E52 - E67:  +12V      -> EXPPROG   +12V to User ROM expansion flash
 E51 - E66:  +12V      -> FA16      +12V to BIOS normal mode
Wire Wraps

 E50 - E27:  MINT0     -> IRQ0      NMI Interrupt
 E23 - E26:  SBXAIRQ0  -> IRQ3      Onboard KISnet
 E105- E145: MINIT     -> PBRESET   So Pnet reset works. MINIT to force OBACLO
 E01:  x x x x x | x x x x x :E10
 E11:  x x x x x | x x x x x :E20

           +-------+ +--------------+
           |       | |              |
 E21:  x x x x x | x x x x x :E30   | E50 - E27 MINT0 -> IRQ0 = NMI
                 |                  | Former keyboard interrupt; do this last!
 E31:  x x x x-x | x-x x x x :E40   |
 E41:  x x-x x x-|-x-x x x x | x x x x x :E55
             |   |           | | | | | |
 E56:  x x x x x-|-x x x x x | x x x x x :E70


 E86 - E88: VCC       -> CPUVCCREF VCC reference for DX4 CPU
 E89 - E90: SPK       -> SPKRDAT   Onboard speaker data

 E80 - E75: GND       -> Color     Color Monitor enable

 E81:  x x x x x :E89
 E82:  x x x-x x :E90

 E71:  x x x x x :E75
 E76:  x x x x x :E80


 E114 - E113: MBCLKO -> MBCLK  Driver Multibus BCLK
 E118 - E117: MCCLK0 -> MCCLK  Driver Multibus CCLK
 E120 - E119: MBINT1 -> MINT1  Triggerable by CPU thru port 75 Bit 0
                               Multibus line to MINT1 whose output is E59

 E113: x-x | x x :E116
       x-x | x-x
       x x | x x
       x x | x x
 E129: x x | x x :E132
         ^   ^
         |   |
 E130: --     -- E131:


 E99  - E95: 3VREG  -> CPUVCC  3.3 Volts for the CPU
 E100 - E96: 3VREG  -> CPUVCC  3.3 Volts for the CPU
 E101 - E97: 3VREG  -> CPUVCC  3.3 Volts for the CPU
 E102 - E98: 3VREG  -> CPUVCC  3.3 Volts for the CPU

 E91:  x x | x x :E94
 E95:  x x | x x :E98
       | | | | |
 E99:  x x | x x :E102


 E103 - E104:  OBACLO -> RESETIN  Multibus Init- Aux reset
 E105 - E145:  MINIT  -> PBRESET  So Pnet reset works. MINIT to force OBACLO
 E107 - E108:  OBACLO -> ACLO

  E103: x-x :E104    Multibus Aux Reset.
+-------x x          E105 - E145 for reset to work.
|       x-x
|       x x
| E111: x x :E112
| _______________________________________________________________
| E146 - E136: MGTEST  -> MGTEST  See sheet 31 in board drawings.
| E151 - E141: MADR23  -> PUP23   Pullup for MADR23
| E150 - E140: MADR22  -> PUP22   Pullup for MADR22
| E149 - E139: MADR21  -> PUP21   Pullup for MADR21
| E148 - E138: MADR20  -> PUP20   Pullup for MADR20
| E133: x x x x x | x x x x x :E142
|             |   | | | | |
| E143: x x x x x | x x x x x :E152
|           |

PNET Modification Instructions 


The original PNET produced an NMI pulse. This pulse was long enough
to be detected by the older 486 CPU cards but the EPC uses the
NMI for another purpose. The PNET interrupt has to be connected to a
regular interrupt. The interrupt pulse could go away before the EPC CPU
had a chance to respond to it.


The PNET NMI pulse was connected to the XILINX control chip on the PNET board. The NMI pulse now latches the INT3 line in the XILINX. This latched NMI is cleared by a read to a specific address in the PNET by the EPC CPU. The INT3 line from the XILINX control chip can be connected to any of the  MultiBus interrupt lines, generally /INT0.


  1. A wire must be added to the board from U16 pin 3 to U13 pin 29. This connects the PNET NMI pulse to the XILINX control chip.
  2. The wire-wrap jumper from JP1 pin 1 to JP1 pin 2 must be removed.
  3. A new wire-wrap jumper must be installed from JP1 pin 2 to JP1 pin 11.
  4. The XILINX boot PROM, U10 must be replaced with a new PROM for  the EPC modification.
Jeff Olsen 4/25/1997 (Year 2000 compliant)

MBCD Modification Instructions 

The EPC board will not do any CAMAC operations with the old MBCD though the new MBCD works fine.

According to Mike Browne, the problem with the old MBCD is that it drives XACK with a signal called AIOWC. AIOWC is a tri-state output that XACK low. The older 486/386 CPU's must have stronger drivers on XACT and over come the MBCD tri-state on the bus.

The reason that the MBCD has AIOWC tied to XACK is to fake an XACK from a non-existant PRIM module. At the end of the CAMAC operation, the MBCD used to do an IOWC write to the PRIM to generate an interrupt. When the PRIM went away, AIOWC was tied to XACK so that the MBCD would not time out on the PRIM IOWC.

The fix then is simply to remove the wire connecting AIOWC to XACK on the MBCD. At the end of the CAMAC Package, the MBCD would have to wait an extra ~6us to time out from the IOWC.