The Beam-Position Monitor (BPM) system for the PEP-II B-Factory at SLAC must measure closed orbit positions for a 3-A multibunch beam and turn-by-turn positions for a low current single bunch injected in a 200-ns gap in the multibunch beam. A system that combines broadband and narrowband capabilities and provides data at high bandwidth was designed. The electronics must also have a very low reflection coefficient, in order to reduce interference from multibunch when the single bunch measurement is required. The system includes the Filter-Isolator Box (FIB) that selects a harmonic of the bunch spacing (952 MHz) and absorbs the other frequency components and the Ring I&Q (RInQ) module. The RInQ is a CAMAC based wideband I&Q demodulator, ADC, and signal processing unit that provides beam position information to the Control System. A calibrator that must work in the presence of beam, correcting for electronic measurement errors, measurement offset, and gain is incorporated on board. This paper describes the system requirements, the electronics design, and the laboratory tests.

A block diagram of the BPM system is shown in Figure 2.1 (y-only BPMs are shown). There are three styles of BPMs x-only, y-only, and xy. Each RInQ module has 8 inputs and can serve 2 xy BPMs or 4 x-only (y-only) BPMs.

The cables are color coded and are connected in the same way at the electrodes, while they do not have the same connection at the FIBs. The transition panel and the RInQ processor keep the same layout (top connector to top connector and so on; except for xy BPMs where blue and green are swapped). The RInQ front panel has LER on the top and HER on the bottom, plus sign on the top and minus sign on the bottom.

In Figure 2.2 the system layout for x-only and y-only BPMs is shown and in Figure 2.3. the system layout for xy BPMs is shown. Note that for both HER and LER the positive x direction points outward from the ring.

The BPM requirements for PEP-II are listed in Table 3.1.

The thermal noise power density generated by a resistor at temperature T (degree K) over the measurement bandwidth B (Hz) is (in an open circuit)

with k = Boltzmann constant. When the circuit is terminated into a resistor of the same value

which corresponds to

In this case the source is capacitive but the cable is lossy enough to behave as a 50 W source. For B = 10 MHz

or

The instantaneous beam current is given by

where Ne is the charge and s is the bunch length. The cosine series for a pulse train with bunch spacing T is

where w₀ = 2p/T. The beam current m frequency component is

if the bunch length is short compared with the wavelength. The voltage at the connector is

where Z is the load impedance and Cpl is the attenuation factor due to the button capacitive coupling. In this case the 952 MHz signal component into 50 W at the connector for T = 1/(238 MHz), s = 30 ps, and Cpl = 1/50 at Ne = 1x10¹¹ ppp is

which corresponds to

The situation for a single bunch is a little different, since the 952 MHz signal is generated by sending the beam through a bandpass filter with 10 MHz bandwidth. In this case the signal is attenuated by 21 dB with respect to the multibunch case. The maximum 952 MHz signal component of the generated burst into 50 W at the connector for 5x10⁸ ppp is

which corresponds to

From the signal and estimated noise figure the expected resolution can be calculated. The position is calculated from the difference over sum of the signal into the positive and negative channels, i.e.,

with b = 33 mm. The resolution is given by

where S/N is the voltage signal to noise ratio. The estimate noise figure is given in Table 3.2.

Thus for single bunch and single pass with N = 5x10⁸

and for multi bunch and single pass with Ne = 1x10¹¹

Other resolution limiting factors are track-and-hold noise and ADC resolution. The specified hold noise is

and the ADC’s resolution due to the LSB is given by the 10-V dynamic range divided by the 2¹⁴ number of counts while the rms error is given by the LSB divided by the quantization error

The total noise due to the combined factors is given in Table 3.3.

An additional limiting factor for the single bunch in the gap is given by the electronics reflection coefficient. The BPM button in fact is a highly reflective source and the measurement accuracy of the pilot bunch is impaired by the multiple reflections through the cable. The problem is illustrated in Figure 3.1.

This problem was addressed and solved from two different sides: the electronics is designed to provide a good load and an isolator is included to reduce reflection from the electronics to the button.

The effect of the reflections is shown in Table 3.4.

The various contributions add up to different values for the LER and HER because of the different cable insertion loss with round trip time equal to the gap length. The total resolution is given in units of mm x ratio, e.g., the HER the resolution is 150 mm if the single bunch and multi bunch have the current or 1.5 mm if the single bunch current is 10% of the multi bunch.

The functionality of the BPM system is primarily set by the software but the processor module (RInQ) does have a DSP on board which can support a variety of functions. There are three basic modes of operation: single-shot executing at 120 Hz, N-turn at the 7-ms rate, and beam abort mode (2000 measurements) at the 7-ms rate. For each mode the processor will return X, Y, and TMIT while for the multi turn modes it also returns s_X, s_Y, and s_TMIT. Each of these modes can be used for single or multi bunch (the processor will contain calibration parameters for each).

The BPM filter-isolator box (FIB) is a passive microwave instrumentation network which performs a filtering, combining, and impedance matching function to broadband, high-frequency signal energy. The input energy sources are 30-ps impulses with peak amplitudes exceeding 500 V.

The FIB consists of traveling wave directional bandpass filters (striplines), constant-resistance low pass filters, hybrid 2-way combiners (Wilkinson), ferrite isolators, and DC bias circuitry. The center frequency is 952 MHz with a passband of 150 MHz. Out of band power is dissipated by 50 W high power resistors. A DC bias of up to 350 V can be put on the BPM buttons to assist in ion clearing.

Requirements and typical performance of a FIB are listed in Table 4.1.

A photograph of the FIB assemblies are shown in Figure 4.1 and a functional diagram is shown in Figure 4.2. Circuit diagrams of the FIB are shown in Figures 4.3-5.

The in-phase and quadrature (I&Q) processing is based on baseband conversion using I&Q demodulators. The amplitude of the demodulated signal is digitally calculated by

where

and the position by

with K a constant determined by the geometry of the buttons.

The formulas are correct in the ideal case but when dealing with real components there are several sources of error to be considered:

Channel gain mismatch produces an error for beam off center and for different beam currents. This is calibrated by ramping the signal power at the channel inputs and measuring the slope of the transverse function. Channel offset mismatch is calibrated by measuring the channel outputs with no signal applied and compensating for the apparent beam position.

Although these two calibration procedures are applicable to all systems using linear processing, phase and amplitude unbalance are typical of the rf processing method chosen for PEP-II. The previous formulas are valid only for an ideal system, when the quadrature phase is exactly 90 deg and both channel amplitudes are the same. The calibrator must measure the amplitude unbalance and the phase unbalance in order to compensate for these errors as well.

A photograph of a RInQ module is shown in Figure 5.1 and a block diagram of the module is shown in Figure 5.2. The rf I&Q demodulator provides demodulated signals to the baseband processor that preprocesses the information to be transmitted to the control system. The calibrator, in conjunction with the local oscillator, permit the processor to be calibrated for offset and gain errors and vector errors.

The rf processor measures the position both for multi bunch, in narrowband mode, and for single bunch, in wideband mode, where the rf burst is generated by the ringing when excited by an impulse. In the latter case the calibrator must sweep through the frequency band, in order to map all the bandwidth.

There are two modes of operation: narrowband and wideband. The narrowband case is used when the multi bunch signal must be measured. The wideband case is used when the single bunch must be measured. In the wideband case there is no rf carrier present, but the rf burst is generated by the single pulse ringing through the bandpass filter.

The requirements are listed in Table 5.1.

The maximum expected input level is in the multi bunch case, for 10¹¹ ppp, and the beam 1 cm off center on the electrode side, where the required resolution is 15 mm. The minimum input is in the single bunch case, for 5x10⁸ ppp, and the beam 1 cm off center on the electrodes opposite side where the required resolution is 1 mm.

The channel-to-channel isolation requirement comes from the fact that two BPMs, one from HER and one from LER, are multiplexed together. It could happen that a single bunch (with low current) from one machine, when the other machine is running at full current. In this case the signal-to-interference should be kept as low as the signal-to-noise ratio to achieve the required resolution.

The BPM rf processor block diagram is shown in Figure 5.3. The coupler accepts the calibration signal, the BPF selects the 952-MHz component, an attenuator and amplifier extend the dynamic range of the circuit, the switch multiplexes HER and LER, the I&Q demodulator and low pass filter amplitude demodulates the input signal, and the T&H acquires the signal to be digitized by the ADC.

The BPM accuracy requirements specify the error to be smaller than 0.25 mm rms, which corresponds to 0.2 dB in the worst case, when the sensitivity is 0.9 dB/mm. The calibrator must be able to measure the electronics errors in order to compensate for these effects. By giving the same weight to amplitude and phase unbalance and channel mismatch, the actual requirements are listed in Table 5.2.

Offset mismatch, also called pedestal, is measured by turning the calibrator off and measuring the apparent beam position.

Gain mismatch is measured by sweeping the calibrator signal power and fitting the single channel transfer function to the best line.

Phase and amplitude unbalance are measured by setting the calibrator frequency to a few kHz (i.e., 70 kHz) off the local oscillator frequency, digitizing at the maximum sampling rate (134 kHz) and then running the amplitude and phase calculation algorithm. This is a fixed frequency curve fitting algorithm, which solves a system of linear equations for amplitude phase and offset.

Since the calibrator must be able to perform also when the beam is present, it works at a frequency different from the beam fundamental. When it is turned on, the local oscillator, which provides the reference frequency to the rf processor for the baseband conversion, is also detuned from the beam frequency. This is particularly important for pedestal calibration when no signal must be applied to the inputs.

Calibration is performed during the gap. The residual beam frequency component is expected to be at –25 dBm in the worst case (30 dBm maximum power and 55 db rf processor return loss. The minimum calibration power is expected to be –40 dBm (21 dBm maximum power and 60 dB programmable attenuation. A 3-pole digital filter can be applied to the digitized data to knock the residual beam signal component to 40 dB below the calibration signal, even though the calibration algorithm is expected to be insensitive to other frequencies.

The wideband mode is calibrated by taking different measurements over the working bandwidth, 932 MHz to 972 MHz.

The digitized values are

where V_I0 and V_Q0 include the amplitude unbalance and e is the quadrature phase error. First correct for gain and offset mismatch

where g is the channel gain and p the channel pedestal. The result is still affected by quadrature phase unbalance.

These formulas, for small phase unbalance, can be approximated by

and

Inverting them

and the channel amplitude can be derived from the sum of squares of these components.

For the case of V₁ not equal V₂ but Df equal zero the calculated amplitude is

which is a sine wave with amplitude equal to half the mismatch amplitude and twice the IF frequency. The measured position error for beam on center is given by

i.e., for a tolerated error of 150 mm accuracy is 2.4% which corresponds to 0.2 dB uncorrected amplitude unbalance.

For the case of V₁ equal V₂ (assume for convenience unity) but Df not equal to zero the calculated amplitude is

which is a sine wave with amplitude equal to half the phase shift and twice the IF frequency. The measured position error for beam on center is

i.e. for a tolerated error of 150 mm accuracy the uncorrected phase unbalance is 1.5 degrees.

A block diagram of the calibrator is shown in Figure 5.4. The calibrator is based on the DDS-driven PLL technique. The reason to choose such a solution are a broad output bandwidth, small step sizes, low phase noise and spurious performance, and minimal complexity and cost. The DDS clock is derived by a prescaler working with the 119 MHz rf reference as an input. It is programmed to provide an output frequency from 9.32 MHz to 9.72 MHz in 7 mHz steps. The PLL final output frequency is 932 to 972 MHz, which is given by the feedback loop divisor that is set at 100.

The digital programmable attenuator allows the power to be swept in 4 dB steps over a 60 dB dynamic range. The medium power linear amplifier with turn off capability provides the required power to the rf processor inputs and guarantees the isolation during normal mode of operation. Switches and power splitters distribute the signal to the eight rf processor inputs. The design of the calibrator allows the amplitude and phase to be swept at different frequencies.

The specifications for the calibrator are listed in Table 5.3.

As shown in the block diagram the prescaler provides the clock to the DDS by dividing the 119 MHz rf reference by 4. The DDS generates a 9.32 to 9.72 MHz signal that is multiplied by 100 in the PLL. The digital programmable attenuator allows the amplitude to be swept. The amplifier optimizes the power for the calibration requirements and the switch and splitters provide the distribution.

In Figure 5.5 a block diagram of the Local Oscillator (LO) is shown.

The LO is based on the same technique as the calibrator and uses the same parts except for the output amplifier. The output amplifier (non-switchable) provides +7 dBm to each of the four I&Q demodulators.

The PEP-II BPM has three basic modes:

A block diagram of the digital hardware of the baseband processor is shown in Figure 5.6.

The DSP Program and Data Memory is 32k x 32. The DSP uses the same memory for program and data. When the DSP boots, data from the Boot Memory is transferred into the Program and Data Memory. The remaining memory can be used for data storage. From CAMAC this memory is 16-bits wide.

The Boot Memory is used to store the power-up code for the BPM as well as any necessary constants. Both CAMAC and the DSP have access to the EEPROM. Care must be taken when writing to the EEPROM since it is a very slow device. From the DSP, a software algorithm must be implemented to insure a 10 ms write time for a single word.

When the DSP is reset, either on a power-up or with an F9A2 command, data from the Boot Memory is moved from the slow speed EEPROM to faster Program and Data Memory.

To download a new program to the EEPROM the DSP must be in the HOLD mode, F9A3. A block of data consisting of a starting address and 64 words of data are written to the BPM via CAMAC. The address of the block must start on a 64 word boundary, A0 through A5 equal zero, and each word must be written within 100 ms of each other. The data is transferred to the EEPROM starting at the supplied address using page-mode write cycles. After the 64 word block has been transferred to the EEPROM, it can take up to 10 ms to finish writing the block into memory. During this time no more data can be sent to the EEPROM. To determine when the BPM is ready for another block of program memory, CAMAC can either wait 10 ms or use the DATA Polling feature of the EEPROM. In this mode, CAMAC reads the last address written. When the data read compares with the data written, the EEPROM block write is finished. Once the download operation is complete a reset, F9A2, will restart the DSP and execute the new program. Single word transfers to and from the EEPROM are permitted and the completion of a write must be insured by waiting 10 ms or DATA Polling as described earlier.

To change the Boot Code CAMAC must first gain access to the Boot Memory by issuing an F29A12 to unlock the module, then an F9A3 to set the HOLD mode. The data in the Boot EEPROM can be altered. When new code has been loaded, CAMAC must boot the DSP by issuing F9A2. This will also release the HOLD state set by the F9A3.

The Dual Port Memory is accessible from both CAMAC and the DSP at the same time. This memory can be used for communication between the DSP and CAMAC. Data available in the Dual Port Memory depends on the mode the BPM is in. The location of the data is determined when the DSP Code is compiled and must be known to the rest of the system for data readout. The following data is passed between the DSP and CAMAC through Dual Port Memory:

Single word messages can be passed between CAMAC and the DSP. When CAMAC writes to address 0x3FFF an interrupt is generated to the DSP (INT1). This interrupt is cleared when the DSP reads this location. If interrupts are not required, this message passing can also be done in a polled fashion. The interrupt bit is also connected to one of the DSP Flag In bits (XF1). The DSP can poll this flag. The DSP can also clear this address and then poll it to see if CAMAC has written a non-zero value.

The timing logic generates a Start signal to the ADC interface. The ADC interface then issues a Start Convert to the ADCs and reads the ADC out, converting the serial data to parallel. When the read out is complete, the ADC will generate an interrupt to the DSP (INT0). The interrupt is reset when the DSP reads any of the ADC values in memory. The interrupt also sets a bit in the DSP Flag In (XF0) that can be polled if interrupts are not required. The ADCs data is available in the DSP memory space.

Once the BPM is configured by CAMAC, the DSP will do all of the data processing and store the results in the appropriate places. The main use of the DSP is to read the 8 ADCs, compute X, Y, and TMIT and store these results in Dual Port Memory to be read out by CAMAC. The timing system will start the ADCs. When the ADCs are finished converting, the DSP will be interrupted. The DSP will then read the 8 ADC values. The ADCs are mapped into the DSP memory space.

The CAMAC block consists of decoders and registers. The registers are accessible via CAMAC operations. The CAMAC functions are:

Reading and witing the Dual Port Memory can take place any time by either CAMAC or the DSP. Normally only the DSP has access to the Boot Memory and the BPM RAM. CAMAC can gain access to the Boot Memory, DSP RAM, and DSP Registers by first putting the DSP in the Hold state via F9A3. When the DSP responds with the Hold Acknowledge, CAMAC will be allowed access to the Boot Memory, DSP RAM, and DSP Registers. This mode is used for changing the Boot EEPROM and doing Peeks and Pokes into the DSP RAM. Since the Registers and ADC are memory mapped, this mode also allows CAMAC direct access to them.

The RInQ Module operates as a memory mapped device. All code, data, control registers, and status registers are contained in memory. The following tables contain a memory map (Table 5.4), details of control registers (Tables 5.5-12), the status register (Table 5.13) and of interrupts (Table 5.14).

Warning: The address space from CAMAC 0x8000 to 0x9FFF and DSP 0x408000 to 0x408FFF is not fully decoded.

There are several control and status registers accessible by the DSP. These registers are used to set up the operating mode of the BPM. The address of these registers are defined in the DSP memory map table.

There are two modes to program the module: local mode through the DSP and remote mode through the CAMAC interface.

In remote mode the module is programmed through the CAMAC interface. It is not possible to memory map the module through CAMAC and for this reason it is necessary to set the address before each write or read operation.

There are eight switches in two sets of four to select LER or HER for section A and B.

The sequence of instructions are:

The local oscillator can be programmed for frequency and phase.

The sequence to set the 16-bit mode is:

The 32-bit word to set the frequency is calculated by

where freq is the desired frequency in Hz and clock is the clock frequency in Hz. Then:

The 12-bit word to set the phase is calculated by

The calibrator can be programmed for frequency, phase, amplitude, and channel.

The sequence to set the 16-bit mode is:

The calibrator is set on with:

The 32-bit word to set the frequency is calculated by

where freq is the desired frequency in Hz and clock is the clock frequency in Hz. Then:

The 12-bit word to set the phase is calculated by

A 4-bit word (Atten) sets the channel attenuation. 0 is no attenuation, F is 60 dB attenuation:

A 4-bit word sets the analog channel.

In local mode the DSP controls all RInQ functions. Communication of results is as described in Section 5 and below.

The following table contains the dual-port memory structure when the DSP code is running.

The following examples show the steps in various operations of the RInQ module from initialization through obtaining results.

HSTA_BPMS_A(00H,00H): 00041H x-only BPMS

HSTA_BPMS_A(01H,00H): 00000H

HSTA_BPMS_A(00H,01H): 00081H y-only BPMS

HSTA_BPMS_A(01H,01H): 00000H

HSTA_BPMS_A(00H,02H): 00041H

HSTA_BPMS_A(01H,02H): 00000H

HSTA_BPMS_A(00H,03H): 00081H

HSTA_BPMS_A(01H,03H): 00000H

HSTA_BPMP_A(00H): 00001H

HSTA_BPMP_A(01H): 00001H

PCMM_A(00H,00H): 00000H

PCMM_A(01H,00H): 00000H

PCMM_A(02H,00H): 00000H

PCMM_A(03H,00H): 00000H

PCMM_A(04H,00H): 00000H

PCMM_A(05H,00H): 00000H

PCMM_A(00H,01H): 00000H

PCMM_A(01H,01H): 00000H

P